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CosmoKramer's avatar
CosmoKramer
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

The RTL netlist is not available error

I completed building fpga image. But when I tried to looking at timing path in rtl viewer, I get error that RTL netlist is not available. I did not set this option - Aggressive Compile Time - as p...
Compilation
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
2 years ago

So you performed a full compilation and you're getting an error that you can't view the design in the RTL Viewer?

If you manually just run synthesis instead of a full compilation, can you view the design in the RTL Viewer?

Is this Standard or Pro?