Forum Discussion
CosmoKramer
Occasional Contributor
Occasional ContributorThe RTL netlist is not available error
I completed building fpga image. But when I tried to looking at timing path in rtl viewer, I get error that RTL netlist is not available. I did not set this option - Aggressive Compile Time - as p...
sstrell
Super Contributor
Super ContributorSo you performed a full compilation and you're getting an error that you can't view the design in the RTL Viewer?
If you manually just run synthesis instead of a full compilation, can you view the design in the RTL Viewer?
Is this Standard or Pro?
