The result is right in emulator mode, but is wrong in FPGA

HRZ,

In response to your comment:

--- Quote Start ---

Yes, if you have multiple kernels running in parallel which read from or write to the same global memory buffer, and read/write order will affect your output, you will likely get incorrect results. Trying to synchronize such kernels using channels will NOT work.

--- Quote End ---

I have not explored this design pattern yet; but is this due to a lack of cache coherence (in the LSUs that are automatically inferred)? Did you ever bring this up with Altera or get a response?