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Altera_Forum's avatar
Altera_Forum
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13 years ago

the problem of timing constraint

Hi: there are a lot of timing violations after synthesizing the SDRAM controller,the constrained clock is 150M. I noticed that the latch clock is about half period faster than the launch clock ,...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Can you attach the report? They both originate at pll_clk, but something is causing huge skew. Either they're not on a global, or one of them goes through a gated clock(that's my guess without seeing the report).