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Altera_Forum's avatar
Altera_Forum
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13 years ago

the problem of timing constraint

Hi: there are a lot of timing violations after synthesizing the SDRAM controller,the constrained clock is 150M. I noticed that the latch clock is about half period faster than the launch clock ,...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

The info messages don't have enough detail. Run TimeQuest and do a report_timing -setup -detail full_path -npaths 2 -pairs_only -panel_name "2 worst paths" -file "worst_paths.txt"

Feel free to attach the text file. I doubt the source and destination are on the same clock. You're using a PLL(hence negative delays) and they always drive a global clock tree, so the skew would be minimal. Anyway, the TimeQuest report will help analyze it better.