The operating frequency of Floating Point ip-cores

Just because you can synthesise it doesnt necessarily mean it will work. The large multipliers are to allow functionality with much slower clocks (like <10MHz)

Have you provided any timing constraints in an SDC file? You need to use timequest to get a timing reeport, and would be run as part of a normal flow.

The data sheet is here:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-iv/cyiv-53001.pdf

From table 1-24, the MAx clock tree speed for the fastest devices is 500 MHz (I cant tell what speed grade device you have). But this is the clock tree, not the logic paths. The routing delays between registers is likely to bring this way down to 200MHz in a well designed system with lots of pipelining and minimal logic between registers.

Why are you trying to acheive such a high frequency? what is your target interface? this usually has a bandwidth limitation and you can work out the system clock speed you require from this.