the "latch" problem

Hello,

I suggest you use V2K style (atleast) and use always @(*) for combinatorial logic blocks. That would resolve your sensitivity list issues. With SystemVerilog you are better off using always_comb. See:

http://www.slideshare.net/fpgacentral/upgrading-to-system-verilog-for-fpga-designs-srinivasan-venkataramanan-cvc

for the slides I presented at FPGACamp in Bangalore on SystemVerilog for FPGA designs.

HTH

Srini

www.cvcblr.com/blog