Forum Discussion
wenna
New Contributor
New ContributorThe increment operation (++) will cause an error.
Consider the following code. Using the i++ operation on line 17 causes an error. module test1 (
input wire clk,
input wire reset,
output reg [7:0] y
);
re...
KennyT_altera
Super Contributor
Super ContributorWe have quite a lot of loop example in the Quartus tools itself.
What you will need to do is open up a blank verilog files, right click and insert template. You will see the loop example that you want to do create.
Do let us know if you have further question? If no, we shall close this thread.
