Forum Discussion
wenna
New Contributor
New ContributorThe increment operation (++) will cause an error.
Consider the following code. Using the i++ operation on line 17 causes an error. module test1 (
input wire clk,
input wire reset,
output reg [7:0] y
);
re...
_AK6DN_
Frequent Contributor
Frequent ContributorThat is an error. You are writing Verilog, not C. Prefix and postfix ++ and -- are NOT valid operators in Verilog.
And in any event the operation i = i++ is nonsensical. Think about it.
I think you meant to write i = i+1 as you did in line 12.
i++ or ++i would also be logically correct, giving the same result as i=i+1 but as I said earlier they are NOT valid Verilog language syntax.
FvM
Super Contributor
Super ContributorUnary incre- and decrement operators are supported in system verilog, but make no sense on assignment RHS.
We don't know if SV syntax has been enabled.
