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Altera_Forum's avatar
Altera_Forum
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16 years ago

The inconsistent results of the Timequest

Dear all, I'm a newbie with Timequest. Currently I'm working with Cyclone III development kit. When I was compiling my system something strange happened. That is every time when I run 'Start Co...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Actually, the top_fsd[*] is the data bus for an very slow asynchronous SRAM, so I think there should be no critical time requirement on these ports. But I don't want to leave unconstrained ports in my design, so I used the hold time in the datasheet report to set the minium input delay. Is it a right way to do it?

Regards,

Dayu