Forum Discussion
Altera_Forum
Honored Contributor
8 years agoA design unit, in the case of Verilog or SystemVerilog, is the "module" you created in your .sv file. The error is saying that ModelSim can't find this design unit, which is odd because it's compiling it just above. There could be something wrong with the instantiation of the myFullAdder01 module in testMyFullAdder01. Can you post some code?