"The design unit was not found" error in Modelsim

Thanks for the reply. I seem to now get some different errors:

# Loading work.Oversample# ** Error: (vsim-10000) Oversample.vo(68): Unresolved defparam reference to '\clock~I ' in \clock~I .operation_mode.# Region: /Oversample# ** Error: (vsim-10000) Oversample.vo(99): Unresolved defparam reference to '\clk16~reg ' in \clk16~reg .lut_mask.# Region: /Oversample# ** Error: (vsim-10000) Oversample.vo(100): Unresolved defparam reference to '\clk16~reg ' in \clk16~reg .operation_mode.# Region: /Oversample# ** Error: (vsim-10000) Oversample.vo(101): Unresolved defparam reference to '\clk16~reg ' in \clk16~reg .output_mode.# Region: /Oversample# ** Error: (vsim-10000) Oversample.vo(102): Unresolved defparam reference to '\clk16~reg ' in \clk16~reg .register_cascade_mode.# Region: /Oversample# ** Error: (vsim-10000) Oversample.vo(103): Unresolved defparam reference to '\clk16~reg ' in \clk16~reg .sum_lutc_input.# Region: /Oversample# ** Error: (vsim-10000) Oversample.vo(104): Unresolved defparam reference to '\clk16~reg ' in \clk16~reg .synch_mode.# Region: /Oversample# ** Error: (vsim-10000) Oversample.vo(114): Unresolved defparam reference to '\clk16~I ' in \clk16~I .operation_mode.# Region: /Oversample

I think I tried that before but as I get even more errors I decided I wasn't heading in the right direction. The errors refer to the only input & output in the source file. I have a very simple test file I am just using to debug the problem at the moment.

Keith.