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moh_late's avatar
moh_late
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3 years ago

The design is right, but the execution is wrong

Good evening and Happy New Year everyone..
Implemented this equation: Attached is a picture with the file
Bit depth: from 8 to 28
Algorithm type: The process of multiplying the highest digits of the multiplier begins with a fixed sum of the partial product and shifts the multiplier to the right by one digit per turn. The multiplier shifts to the left
This build is on Quartus II 9.1sp2 Web Edition
But when executing, the error appears
Error: Illegal name "A[27]" -- pin name already exists
Error: Illegal name "A[27]" -- pin name already exists
Error: Illegal name "A[27]" -- pin name already exists
Error: Can't elaborate top-level user hierarchy
Error: Quartus II Analysis & Synthesis was unsuccessful. 4 errors, 1 warning
Error: Peak virtual memory: 235 megabytes
Error: Processing ended: Sun Jan 01 19:56:31 2023
Error: Elapsed time: 00:00:00
Error: Total CPU time (on all processors): 00:00:01
Error: Quartus II Full Compilation was unsuccessful. 6 errors, 1 warning

General

4 Replies

  • Jocelyn_Intel's avatar
    Jocelyn_Intel
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hello, @moh_late.

    Thank you for posting on the Intel® communities.

    We understand that you have an inquiry about Intel® Quartus II 9.1sp2 Web Edition.

    We have a forum for those specific products and questions so we are moving it to the Intel® Quartus® Prime Software Forum so it can get answered more quickly.

    Best regards,

    Jocelyn M.

    Intel Customer Support Technician.


  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    3 years ago

    In your schematic, you've got an input named "A[27],A[27],A[27],A[27..3]". That doesn't make any sense.

    • moh_late's avatar
      moh_late
      Icon for New Contributor rankNew Contributor
      3 years ago

      thank you very much!
      What should be done to correct it, please, according to the equation attached in the files

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    3 years ago

    I don't know about that, but you need to name busses and individual signals, including I/O, appropriately. If you're trying to concatenate multiple signals together into a single bus, you'll need logic to do that.