The basis about library

Simulation does not use VHDL directly - it needs to compile the design into some binary to actually run, plus it will do some optimiasation so it doesnt take 3 weeks just to simulate a flip flop. What is in these files, you'll have to ask the vendor.

Kaz: there is no need to have a package in a library. You can just use direct instantiation. The library names come from the tool, not the VHDL (you reference them in VHDL, but you dont create them in VHDL). This way, every library can reference itself via "work".

Lets say we have 2 libraries:

LibA - with entities entA1 and entA2.

from within lib A I can access either entity via work.EntA1, or work.entA2 etc.

from within another library, I would call up libA.entA1. But I cannot call LibB.entB1 inside library A, because it hasnt been compiled yet.