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Thanks very much, kaz. So the libraries are used in simulation are vendor libraries, and I think they are originally HDL files, but they need to be compiled before used.
What are libraries used in VHDL file? Like IEEE library, I think they are vendor libraries too.
The user libraries are created by ourselves, but I don't know when I need it.
For Vendor libraries, yes, I don't need to know what exactly they are after they are compiled. But I am curious is: what are they as HDL files? Are they just HDL design files for IP (modules in Verilog, entity in VHDL) wrote by vendors like the design files we wrote? Do we need them both in synthesis and simulation?
Thanks very much.
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Well the standard vhdl libraries may be viewed as vendor though they belong to IEEE and have their specific names across all vendors. They are based on HDL before compilation. vendor specific libraries carry whatever chosen name is given to them e.g. lpm_pack.vhd & altera_mf_components.vhd etc.
After compilation they are not HDL (some other unreadable files).
User libraries are based on package declarations for your various project wide types, constants, functions...etc. They have to be compiled as well and in quartus they are compiled with your other HDL units by adding them to project just like other HDL modules.
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