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I am always confused by the usage and definition of library. Although currenly it looks like it did not affect my FPGA design and development, but I am eager to have a clear understanding about them. In this thread, I want to be clear about main two issues:
1. Library for simulation
2. Library for VHDL
(1) As I know, there is no concept of library in Verilog. For simulation, if we use Modelsim-Altera, we can see the list of precompiled libraries when we open Modelsim. If we use Modelsim SE or DE, we can firstly compile the libraries provided by Altera， Xilinx, then we can see the compiled libraries in Modelsim. These libraries usually are named by components, IPs, and have both VHDL and Verilog versions. So my first question is: what is inside of these libraries? Is the path where to get the relevant IP design files (HDL files) ?
(2) For libraries in VHDL, as I know, the library is used to tell the path, so if there is two modules with exact same name but they are in different libraries, then the world is still good. But I am curious when we use libraries in VHDL, we just write a command at the beginning of VHDL file. Where is the file of library? What is the extension of the VHDL library file?
Thanks very much.
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You need first to make a distinction between vendor library and user library.
And in the case of vendor library you need to make distinction between HDL based files in folders named library and precompiled library.
For example if you look around you will see a folder named ieee that contains vhdl code. This is not what quartus or Modelsim will look at. Instead Quartus looks at precompiled version of it which - I believe - is done as part of installation and it knows where they are(not visible to user).
On the other hand ModelSim gives(or may) visibility and choice to where it is to be precompiled to and there you see some strange files with extensions like .dat, .dbs ..etc. I don't need to know what these do and I view them as precompiled intermediate products for final netlist with your code.
For user library in quartus you can just add it to project as any other vhdl module or apply use statements to specify target.
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