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Honored ContributorTestbench
Hi,
I have a strange simulation results from ModelSim Altera Web edition. I wrote a testbench to test an ALU. When I compared the result with Quartus II simulation, they are not the same even though I have exactly the same inputs to the ALU. Any comments on this? Thanks.library ieee;
use ieee.std_logic_1164.all;
use work.BasicArith.all;
Entity test_alu is
port(alu_out : out std_logic_vector( 7 downto 0));
end;
architecture testbench of test_alu is
component alu
port( a_in : in std_logic_vector(7 downto 0);
b_in : in std_logic_vector(7 downto 0);
op_code : in std_logic_vector(2 downto 0);
alu_out : out std_logic_vector(7 downto 0));
end component;
signal sig_a : std_logic_vector(7 downto 0);
signal sig_b : std_logic_vector(7 downto 0);
signal sig_op : std_logic_vector(2 downto 0);
For U1:alu use entity work.alu(behavior);
begin
U1:alu port map(a_in => sig_a, b_in => sig_b, op_code => sig_op, alu_out => alu_out);
process
begin
sig_a <= "01001011";
sig_b <= "00101010";
sig_op <= "000";
wait for 10ns;
sig_op <= "001";
wait for 10ns;
sig_op <= "010";
wait for 10ns;
sig_op <= "011";
wait for 10ns;
sig_op <= "100";
wait for 10ns;
sig_op <= "101";
wait for 10ns;
sig_op <= "110";
wait for 10ns;
sig_op <= "111";
wait for 10ns;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
PACKAGE BasicArith IS
component alu is
port( a_in : in std_logic_vector(7 downto 0);
b_in : in std_logic_vector(7 downto 0);
op_code : in std_logic_vector(2 downto 0);
alu_out : out std_logic_vector(7 downto 0));
end component;
END BasicArith;
----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
ENTITY alu IS
port( a_in : in std_logic_vector(7 downto 0);
b_in : in std_logic_vector(7 downto 0);
op_code : in std_logic_vector(2 downto 0);
alu_out : out std_logic_vector(7 downto 0));
END alu;
architecture behavior of alu is
signal temp: std_logic_vector(7 downto 0);
begin
process(op_code)
begin
case op_code is
when "000" => temp <= a_in + b_in;
when "001" => temp <= a_in + b_in;
when "010" => temp <= a_in - b_in;
when "011" => temp <= a_in - b_in;
when "100" => temp <= a_in and b_in;
when "101" => temp <= a_in and b_in;
when "110" => temp <= a_in or b_in;
when "111" => temp <= a_in or b_in;
when others => temp <= (others => 'Z');
end case;
if op_code(0)='1' then
alu_out <= To_StdLogicVector(To_bitvector(temp) sll 1);
else
alu_out <= temp;
end if;
end process;
end behavior;
