--- Quote Start ---
process(op_code)
begin
case op_code is
when "000" => temp <= a_in + b_in;
when "001" => temp <= a_in + b_in;
when "010" => temp <= a_in - b_in;
when "011" => temp <= a_in - b_in;
when "100" => temp <= a_in and b_in;
when "101" => temp <= a_in and b_in;
when "110" => temp <= a_in or b_in;
when "111" => temp <= a_in or b_in;
when others => temp <= (others => 'Z');
end case;
if op_code(0)='1' then
alu_out <= To_StdLogicVector(To_bitvector(temp) sll 1);
else
alu_out <= temp;
end if;
end process;
--- Quote End ---
You need to add more signals to your sensitivity list. (a_in, b_in and temp etc) Basically any signals that affect signals assigned in the process.
Modelsim is very picky about sensitivity lists. Quartus may not be so picky as they are often ignored in synthesis.
Hence in Modelsim your process may nor run when a_in and b_in change but opcode remains constant.
Honored Contributor
