tco question on VHDL

Elpuri had already answered well. I will add this:

You don't mean Tco really. Tco is the clock edge to output transition time for a given register.

You probably mean one clock latency needed, so just add one more register at the output as follows:

ENTITY count_tia IS
    PORT
    (
        clock:         IN STD_LOGIC;
        sload:         IN STD_LOGIC;
        data:         IN integer RANGE 0 TO 127;
        result:        OUT integer RANGE 0 TO 127
    );
END count_tia;
 
ARCHITECTURE rtl OF count_tia IS
    SIGNAL result_reg : integer RANGE 0 TO 127;
BEGIN
    PROCESS (clock)
    BEGIN
        IF (clock'event AND clock = '1') THEN
 
            IF (sload = '1') THEN
                result_reg <= data;
            ELSE
                result_reg <= result_reg + 1;
            END IF;
 
            result <= result_reg;
 
        END IF;
    END PROCESS;
 
END rtl;