tco question on VHDL

Well I'm just a hobbyist so take my advice with a grain of salt, but I've understood that generating useless logic to achieve a delay is just asking for troube. You have to know the architecture well and even if you get it right, it will still be technology dependent (synthesizing for some other device will likely produce different results).

What you could do is still make it synchronous. If the device you're targeting has PLLs, you could use one to generate a 100MHz clock inside the device. Then you could use that 100MHz clock to clock a register that would create a 10ns delay.

You should of course take into account that the I/O buffers of the device will have delays of their own (and you should probably synchronize the input signals if they're asynchronous to the clock).