Tco Constraints

I may have mis-understood the Quartus literature when it says tco applies from an input pin to an output pin; but I had thought that the input pin is your clock and the output pin is obviously your signal output - i.e. tco is the time between the clock edge and output changing. Ultimately the clock will come from an input pin - hence the Quartus literature saying it applies to input and output pins.

The slew rate limiting as far as I know is to limit the rise (and fall) times of outputs. Basically the edge slope is the critical parameter when you're considering signal integrity on the board - forget about the frequency of clocks etc - it's the slope of the transitions on those signals that contains the high frequency stuff which causes you problems. If you're not running signals at stupid MHz then you don't need them to transition that quickly - so if it's giving you grief you can limit the slew rate. Quite often this is done as standard to avoid signal integrity / EMC issues rather than finding you need it and then turning it one.

My advice would be to get a scope out and see if the signals are suffering with ringing, overshoot etc without the slew rate limit. If they're OK and they don't appear to be upsetting anything else then you're probably safe to leave the slew rate limit off.