Tcl Error in Timing Analysis phase using LVDS SERDES RX IP

Hi,

Kindly change the below:

In the file:

verilog_code/adc/adc_lvds_rx/altera_lvds_core20_191/synth/sdc_util.tcl

Change this line:

set fclk_name "${lvds_instance_name}${RX_NON_DPA_FCLK_TRAIL}"

To this line:

foreach_in_collection lvds_node [get_nodes -nowarn "$lvds_instance_name|*|fclk"] { set fclk_name [get_node_info -name [get_edge_info -src [get_node_info -clock_edges [lindex $lvds_node 0]]]]; break }

Note that if the IP is regenerated, you have to update this line in the SDC again.

Thanks.

Best regards,

KhaiY