Tcl Error in Timing Analysis phase using LVDS SERDES RX IP

It is not a typo, it is intentional.

I'm driving two LVDS SERDES RX IP cores with the same clock because I do not have space for other pins (and as you said only 1 PLL for every bank), so two ADCs are read with the same clock.

Quartus 19.1 correctly understands this and generates two instances of LVDS IP connected to the same clock that shares the same PLL.

Do you suggest that I have to try and merge the two LVDS cores that have the same clocks, i.e. from 2 LVDS of 8 bits to 1 LVDS of 16 bits, for example?