Sytem Verilog one-hot selection

According to the SV LRM, a tool can issue a warning if the case expression doesn't match a case item in a unique/priority case. That's it. It says nothing about assigning a "don't-care" value to all the variables assigned inside the case statement (and what about two-state variables that don't have x/z?) The variable will hold its previous value, i.e. the LRM says nothing about the keyword changing the simulation semantics. So I'm sticking to my guns here and calling it a flaw. :) It would be one thing if the LRM made a proclamation about synthesis behavior, but it only discuses simulation behavior.

Still, I imagine Altera and most other vendors will follow the general consensus among users. I'd file a service request if you feel strongly about the issue. You have a point - for the savvy user, it's annoying that Quartus II won't assume full_case for unique/priority case statements. The logic of, "Well, it may cause a simulation/synthesis mismatch and people may not be aware" isn't exactly compelling to me and I'm the one making the argument. :) I re-iterate my point: it would have been better for the LRM to make it a run-time error.