Sytem Verilog one-hot selection

This is a good discussion!

Let's focus on the simulation side. How exactly would a simulator honor the full_case implication of the unique/priority keywords? Here's an example:

module unique1(input  sel, input a, b, c, d, output reg o);
   always_comb
	 begin
		o = d;
		unique case(sel)
			2'b01: o = a;
			2'b10: o = b;
			2'b11: o = c;
 	      endcase
	 end
endmodule

What would happen in simulation if sel == 2'b00? I ran this example in Modelsim 6.2f SE but it gave me the following:

# ** Warning: unique1.v(6): (vlog-62) SystemVerilog keyword 'unique' is not currently supported.

Still, what would you expect to happen if a simulator supported the unique keyword, i.e. what value should o have after executing the case statement. Seems like it should be o == d, which is exactly how it simulates in Modelsim without unique support. I ran the example in Quartus II 7.2 SP1 and, in fact, it matches Modelsim.

Seems like it's a flaw in the standard. If a synthesis tool honors the full_case implication of unique/priority, it creates the possibility of a simulation-synthesis mismatch. True, the same argument applies to the primary meaning of unique/priority, too! But the primary meaning is more obvious, I feel. I understand that unique means parallel_case and priority means no parallel_case. But it's not obvious that unique and priority both imply full_case, so it's more dangerous for a synthesis tool to rely on that implication, i.e. because it may not be a legitimate expression of the designer's intent. For sure, the unique/priority keywords do absolutely nothing to change the semantics of the case statement in simulation.

The SV standard should have made it an error for a unique case statement to have overlapping case items and for a unique/priority case statement to be incomplete, e.g. have a value for the case expression that doesn't match a case item.

I do agree with you that Quartus II should be clear that it ignores the full case implication, for it currently issues this warning for my example:

Warning (10270): Verilog HDL Case Statement warning at unique1.v(6): incomplete case statement has no default case item