Sytem Verilog one-hot selection

Hi,

I know you are much more expert than me, but please, I beg to differ once again.

In first place I assume you are just guessing about Quartus doing this on purpose and not being a bug. Or do you have some internal info about this?

And again, even if that is the case, I would expect this to be explicitely documented, may be even to issue a warning.

I don't think the latches are for the purpose of matching the simulation. The latches are a direct consequence of not inferring a full case. There is no need to infer latches to match simulation, because most simulators (hopefully) will follow the SV LRM standard. I guess this is not the whole industry going against the standard, or is it ? :)

It doesn't make any sense to force you to use synthesis attributes for accepting a potential difference with synthesis and simulation. The whole point of the SV unique keyword is precisely to avoid this difference. It is a language keyword, not an attribute. Both synthesis tools and simulators would (should) see it.

I don't see why you are saying they are preserving the "defined" semantics of the design. The semantics are defined by the standard and by the implementation documentation. Not by what you and me (or Altera for that matter) might like. So I would say that the defined semantics is a full case.