Sytem Verilog one-hot selection

The latches are an attempt to match what would actually happen during simulation if your case expression didn't match an explicit case item. Your variable would hold its previous value. In that sense, Altera is simply trying to match the simulated behavior of the design as much as possible. They aren't simply tossing the standard aside flippantly; they are preserving the defined semantics of the design. They chose to require you to use the full_case attribute to force the potential simulation/synthesis difference.