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Altera_Forum
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18 years ago

Sytem Verilog one-hot selection

Aren't the new System Verilog case specifiers (unique/priority) supposed to avoid the need of using the synthesis attribute "full_case" ? No matter what I do, I cannot get a one-hot optimized s...
Altera_Forum's avatar
Altera_Forum
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18 years ago

Hi HDL Guru,

I'm not sure I follow your logic. Yes, I might agree that the term "unique" might not be the best choice to imply a full case. But like it or not, that's the standard. And it doesn't make much sense to me that Altera would, on purpose, go against the standard because it doesn't like the keywords selected by the standard.

It seems more like a bug. If Altera would prefer an "unique" behavior for the "unique" keyword, then at the very least this should be clearly documented (I would actually add a configuration option).

And I'm not sure it is safer. It is not just an issue of missing an optimization. It infers latches.