Sytem Verilog one-hot selection

Looks like Quartus II only implements the parallel_case semantics of the unique keyword and not the full_case. To me, it's not natural for unique and priority to imply full_case, even though the LRM does define it that way. The tool probably considers it safer to avoid relying on the full_case implication. Sure, it misses an optimization, but it also avoids an unintentional change to the design semantics. If the LRM had made it an error rather than a warning to have a case value that's not covered by an explicit case item, then it would be easier to utilize the full_case semantics. The LRM should have defined a full keyword to avoid all this confusion. :)