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Altera_Forum
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18 years ago

Sytem Verilog one-hot selection

Aren't the new System Verilog case specifiers (unique/priority) supposed to avoid the need of using the synthesis attribute "full_case" ? No matter what I do, I cannot get a one-hot optimized s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

They do are supported, I'm using Quartus 7.2. At least both the help and the manual claim they are supported. Some tests indicate it correctly infers "parallel" cases thanks to the "unique" keyword. But it doesn't seem to infer a "full" case.