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Altera_Forum
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18 years ago

Sytem Verilog one-hot selection

Aren't the new System Verilog case specifiers (unique/priority) supposed to avoid the need of using the synthesis attribute "full_case" ? No matter what I do, I cannot get a one-hot optimized s...
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Altera_Forum
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18 years ago

If they are supported by the tools, then they probably would do that. But they might not yet supported by the tools (presumably Altera quartus_map in this case), or might not be supported by the tool version that you have.