Honored ContributorIt seems like Quartus 16.0 will choke on SystemVerilog "unique if" statements. Could somebody else confirm this, or are there additional SystemVerilog options which can be set in order to support it?
Thanks!
Honored ContributorQ16.0 only supports the following SV constructs:
http://quartushelp.altera.com/16.0/index.htm#hdl/vlog/vlog_list_sys_vlog.htmHonored ContributorQuartus Prime Pro(which I believe only supports Arria 10) has a new front end HDL interpreter that supports a lot more than the old one. I don't have exact details on what it supports, but would expect this to be supported.
Honored ContributorHonored ContributorGood point. I'll have to check that out.
