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Altera_Forum
Honored Contributor
Honored ContributorSystemVerilog "unique if" not supported in Quartus?
It seems like Quartus 16.0 will choke on SystemVerilog "unique if" statements. Could somebody else confirm this, or are there additional SystemVerilog options which can be set in order to support it?...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Q16.0 only supports the following SV constructs: http://quartushelp.altera.com/16.0/index.htm#hdl/vlog/vlog_list_sys_vlog.htm --- Quote End --- Thanks! That says "Supported (unique/priority supported only on case statements)" which basically means that unique if is not supported.
