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Altera_Forum's avatar
Altera_Forum
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9 years ago

SystemVerilog "unique if" not supported in Quartus?

It seems like Quartus 16.0 will choke on SystemVerilog "unique if" statements. Could somebody else confirm this, or are there additional SystemVerilog options which can be set in order to support it?...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Quartus Prime Pro(which I believe only supports Arria 10) has a new front end HDL interpreter that supports a lot more than the old one. I don't have exact details on what it supports, but would expect this to be supported.