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Altera_Forum
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11 years ago

[SystemVerilog] Passing "inout" thru verbatim

Hi all, I have an Altera DE2-115 board and am working on interfacing with the asynchronous static RAM chip. I have gotten a simple test harness working, but only if it is the top-level entity. ...
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Altera_Forum
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11 years ago

Dave!!! You solved in 36 minutes (probably really more like 30 seconds) what I have been banging my head against for two days (probably 6-8 hours of real time).

Thank you so much.

For the record: both of your suggestions work in the top level module declaration: 


inout  SRAM_DQ,
inout wire logic  SRAM_DQ,

Needless to say I will have copious comments in my code describing this oddity.

Cheers!