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Altera_Forum
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11 years ago

[SystemVerilog] Passing "inout" thru verbatim

Hi all, I have an Altera DE2-115 board and am working on interfacing with the asynchronous static RAM chip. I have gotten a simple test harness working, but only if it is the top-level entity. ...
Altera_Forum's avatar
Altera_Forum
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11 years ago

I believe the compiler is incorrectly classifying inout logic [15:0] SRAM_DQ, as a variable, not a net declaration. Try inout wire logic [15:0] SRAM_DQ, or inout [15:0] SRAM_DQ, . Verilog and SystemVerilog are both rife with implicit declaration madness.