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Altera_Forum's avatar
Altera_Forum
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18 years ago

SystemVerilog in SOPC Builder

I am trying to add a component that's written in systemverilog to sopc builder 8.0. Quartus compiles and runs this code on the hardware just fine, but sopc refuses to even use the file. It seems to be calling the compiler with the wrong settings. Anyone know how to fix it?

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    ok, I figured it out. You have to add the following synthesis directive at the top of the file:

    // synthesis VERILOG_INPUT_VERSION SYSTEMVERILOG_2005