Altera_Forum
Honored Contributor
Honored ContributorSystemVerilog feature in Verilog files
assign data_bus = wr_mem ? ac : 'z;
Error (10839): Verilog HDL error at cpu.v(31): 'z is a SystemVerilog feature Is it strong file typing? Can it be relaxed?Forum Discussion
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Altera_ForumIf you want to use SystemVerilog, you can change the file extension from .v to .sv.
'z,'x, '1, and '0 are SystemVerilog features that fill the value with the bit you specify based on the context of the expression its used in. In this case, the width of data_bus sets the context, so if data_bus is a 32 bit type, it is the same as writing 32'bz, which is what you must write if using Verilog.
