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Petrov1's avatar
Petrov1
Icon for New Contributor rankNew Contributor
5 years ago
Solved

SystemVerilog Error

Hello guys, I received error: Error (12061): Can't synthesize current design -- Top partition does not contain any logic. I am trying to test a verilog module in system verilog. Can anyone please h...
  • sstrell's avatar
    sstrell
    5 years ago

    This looks like a simulation testbench so at least some of it (most of it actually) would not be synthesizable (initial block, delays, $display, etc.).

    But if you have synthesizable designs with this error, make sure the .v or .sv file is added to the Quartus project, the name of the file matches the name of the module (test_validin.sv), and that the top-level entity selected in the project matches the name of the module (test_validin in this case).

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
5 years ago

This looks like a simulation testbench so at least some of it (most of it actually) would not be synthesizable (initial block, delays, $display, etc.).

But if you have synthesizable designs with this error, make sure the .v or .sv file is added to the Quartus project, the name of the file matches the name of the module (test_validin.sv), and that the top-level entity selected in the project matches the name of the module (test_validin in this case).