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Altera_Forum's avatar
Altera_Forum
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11 years ago

SystemVerilog error 10748

Hi all,

I am using SystemVerilog to handle a 3-dimensional array. My code is as follows. 


module sub_bytes();
reg  word_stream_reg = '{'{8'hFF,8'hA4},'{8'h50,8'hC6}};
reg  test = word_stream_reg; 
endmodule

I get this error: Error (10748): Verilog HDL error at sub_bytes.v(6): expression in variable declaration assignment to test must be constant

I spent about 4 hours but could not find the reason for this error. I would be grateful if anyone could assist me in this.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Even if some tools allow it, it is a very bad programming practice to initialize a static variable with a another static variable. This is refereed to the "static initialization fiasco" in many programming languages. Outside of a procedural context, there is no defined ordering of static initializers.

    Assigning a constant value to a variable does not make that variable a constant. It's still a variable as far as the compiler is concerned.

    What you probably want to do is use a parameter instead of a variable. 

    parameter logic  word_stream_reg = '{'{8'hFF,8'hA4},'{8'h50,8'hC6}};

    Note: Since you are using SystemVerilog, use logic instead of reg.