SystemVerilog error 10748

Even if some tools allow it, it is a very bad programming practice to initialize a static variable with a another static variable. This is refereed to the "static initialization fiasco" in many programming languages. Outside of a procedural context, there is no defined ordering of static initializers.

Assigning a constant value to a variable does not make that variable a constant. It's still a variable as far as the compiler is concerned.

What you probably want to do is use a parameter instead of a variable.

parameter logic  word_stream_reg = '{'{8'hFF,8'hA4},'{8'h50,8'hC6}};

Note: Since you are using SystemVerilog, use logic instead of reg.