systemC testbench in modelsim and simulation problem

Sorry if this is not the correct place to post my question, but I really need help, as I am a total newbie in systemC.

I have a question about using modelsim to simulate systemC files .

I am not sure how to build the test bench for programs in systemC and how the simulation

Process works.

For example I have a program that I built in systemC – mux_2x4 which

Has 2 inputs of 4 bits each and a 1 bit control that according to its value the output

Receive one of the 2 inputs.

This is the program:

# include "systemc.h"

SC_MODULE (mux_2x4)

{

sc_in < sc_lv<4> > din0, din1;

sc_in < sc_logic > ctr_mux;

sc_out < sc_lv<4> > dout;

void main_proc();

SC_CTOR (mux_2x4)

{

SC_METHOD(main_proc);

sensitive << din0 << din1 << ctr_mux;

}

};

void mux_2x4::main_proc()

{

if (ctr_mux.read() == SC_LOGIC_0)

dout.write(din0.read());

else if (ctr_mux.read() == SC_LOGIC_1)

dout.write(din1.read());

}

I want to build a systemC testbench for this program and run a simulation on modelsim.

Also what can u do with H files since the compiler (unlike Visual studio) will not compile them

Like the cpp files. Can anyone help me please ?

Thanks in advance ,

Dor