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Altera_Forum's avatar
Altera_Forum
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14 years ago

system console model is invalid

I have been trying for some time now to get a very basic Nios design to run. I have built the .sof and downloaded it to the Stratix-III. I have built the BSP and .elf file to simply control the LEDs on the dev kit board. But no matter what I try, I always get the dialog box that pops up with the following message:

"The system console model is invalid. Cannot launch."

I see one other thread that discussed this but I do not see any real conclusions. Does anyone have any idea what the problem can be?

Many Thanks....

13 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    How are you invoking system-console (from a command shell, from Eclipse, from qsys, etc.)? Try starting it another way and see if the result is the same.

    What operating system are you using? What version of Quartus/Nios?
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    I have been trying for some time now to get a very basic Nios design to run. I have built the .sof and downloaded it to the Stratix-III. I have built the BSP and .elf file to simply control the LEDs on the dev kit board. But no matter what I try, I always get the dialog box that pops up with the following message:

    "The system console model is invalid. Cannot launch."

    I see one other thread that discussed this but I do not see any real conclusions. Does anyone have any idea what the problem can be?

    Many Thanks....

    --- Quote End ---

    I have the same error， do you konw the solution of the problem??
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    try to set the hooks in the run configurations

    ignore sys id

    ignore time stamp
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    try to set the hooks in the run configurations

    ignore sys id

    ignore time stamp

    --- Quote End ---

    thanks!!!

    it works:-P
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I have the same problem but it persists even with these options.

    When I set 'ignore sys id' and 'ignore time stamp' the system console error disappears but a new one appears instead (Verify failed between address ...).

    I am using Quartus 11.1 and I am not sure about how to use the system id in this version,

    Thanks in advance.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    It is a bad idea to disable the ignore sys id and ignore timestamp options. If you have an error with those options enabled it means that you have an inconsitency in your project, that your compiled software and uploaded FPGA image are based on different definitions.

    Try to recompile everything (hardware and software) and be sure that you are uploading the correct .sof FPGA image and software.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I've already done that lots of times.

    I was working with Quartus 9.1 and this error didn't appear except in the situations you mention, but now with Quartus 11.1 it happens even after recompile everything and uploading all again.

    Maybe I'm doing something wrong in Qsys with the sdram connections.

    Thanks
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    No if it were a problem with the sdram then you'd get a verify fail. The only reasons I can think of for a system id / timestamp error is a mismatch between the hardware and the software.

    Each time you generate the SOPC Builder / QSys project, a new ID and timestamp are written in both the .sopcinfo file, that is read by your software IDE for the ID/timestamp check, and in the generated .v/.vhd files, which are read by Quartus when it compiles the design.

    If you have a ID/timestamp error, it means that the values the software IDE is trying to read from the FPGA aren't those that have been read from the .sopcinfo file. There is no other reason I can think of.

    Did you regenerate your SOPC/QSys project when you moved to Quartus 11.1? Are you sure the software BSP is pointing to the correct .sopcinfo file? Are you sure Quartus isn't generating a time limited sof, and not the image you are uploading to the FPGA?
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I think this error is a bug in 11.0 which has been fixed in 12.0. Can you try with the later version?

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I am getting the same "Problem Occurred" and I am not even trying to use the system console. I am just trying to download and run a new .elf. I have a system ID module; it matches the ID and timestamp in system.h. I am using Quartus II 12.0. From Eclipse SBT 12.0, I select Run -> Run Configurations... and then highlight <project> Nios II Hardware configuration. Under the Project tab, I have the project name selected and the correct Project ELF file name. Under the Target Connection tab, I have refreshed the connections, verified the System ID Properties, disabled the 'Nios II Console' view, NOT checked the ignore System ID checks, and checked all the Download options (Download ELF to selected target system, Start Processor, Reset the selected target system). I don't know why there is a "Debugger" tab for a "Run" configuration. There is not an option for no debugger, so I kept the default "Altera CDI GDB Debugger." For the last two tabs, I kept the defaults. When "Run" is clicked, it does some things, says it is launching the Nios II Hardware configuration, then at 60% I get the Problem Occurred... The system console model is invalid. Cannot Launch.

    My Nios design runs fine when when the data and instruction memories are preloaded with the generated .hex files. So right now, every time I make a Nios code change, I have to recompile and reconfigure the FPGA!

    I have also tried downloading from the Nios II command shell. I type

    nios2-download -g <project>.elf

    and I get:

    Using cable "USB-Blaster [USB-0]", device 1, instance 0x0

    Processor is already paused

    Initializing CPU cache (if present)

    OK

    Downloading 32KB in 0x5s (64.0KB/s)

    Verifying 00000000 ( 0%)

    Verify failed between address 0x0 and 0x6273

    Leaving target processor paused

    At this point, if I use the CPU reset button on my Cyclone IV GX demo board to reset the processor, it runs the new code. However, some of the program data seems to be in the separate data memory, which I don't think was downloaded (because the instruction memory download failed?), so this may not always work.

    Finally, does anybody know what the sc_inf_0 module is that keeps showing up in the example designs? I can't find any information about it anywhere.