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Altera_Forum's avatar
Altera_Forum
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14 years ago

system console model is invalid

I have been trying for some time now to get a very basic Nios design to run. I have built the .sof and downloaded it to the Stratix-III. I have built the BSP and .elf file to simply control the LEDs ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

No if it were a problem with the sdram then you'd get a verify fail. The only reasons I can think of for a system id / timestamp error is a mismatch between the hardware and the software.

Each time you generate the SOPC Builder / QSys project, a new ID and timestamp are written in both the .sopcinfo file, that is read by your software IDE for the ID/timestamp check, and in the generated .v/.vhd files, which are read by Quartus when it compiles the design.

If you have a ID/timestamp error, it means that the values the software IDE is trying to read from the FPGA aren't those that have been read from the .sopcinfo file. There is no other reason I can think of.

Did you regenerate your SOPC/QSys project when you moved to Quartus 11.1? Are you sure the software BSP is pointing to the correct .sopcinfo file? Are you sure Quartus isn't generating a time limited sof, and not the image you are uploading to the FPGA?