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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

system console model is invalid

I have been trying for some time now to get a very basic Nios design to run. I have built the .sof and downloaded it to the Stratix-III. I have built the BSP and .elf file to simply control the LEDs ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

It is a bad idea to disable the ignore sys id and ignore timestamp options. If you have an error with those options enabled it means that you have an inconsitency in your project, that your compiled software and uploaded FPGA image are based on different definitions.

Try to recompile everything (hardware and software) and be sure that you are uploading the correct .sof FPGA image and software.