Hi , for a university project I programed ( VHDL) some program to test FPGA errors under very noisy environments . the structure is built of (pseudo) random number generator--->simple ALU *2----> comparator to compare the results from the 2 ALU'2---> the output is one bit error when the results are not the same. when I compile it in QUARTUS I see in the compilation report that the device only use the pins and no logic/LUT or anything else is being used. do you have any idea why? / how to fix it? thanks ...

--- Quote Start --- Hi , for a university project I programed ( VHDL) some program to test FPGA errors under very noisy environments . the structure is built of (pseudo) random number generator--->simple ALU *2----> comparator to compare the results from the 2 ALU'2---> the output is one bit error when the results are not the same. when I compile it in QUARTUS I see in the compilation report that the device only use the pins and no logic/LUT or anything else is being used. do you have any idea why? / how to fix it? thanks ... --- Quote End --- Hi, without seeing the source code it is difficult to say. The synthesis tool has removed your logic. This could happen e.g no output depends on the inputs, the clk is not connected, a reset is not connected ...... Kind regards GPK

OK , I think you are right. there is no reset , but I have some warning about the clock that it runs no logic. how do i define it to run logic? ( the processes in my design are driven with the clock so I don't really realize why "it runs no logic" ?) thank for your quick response....

you will have to show us the code.

ok , I tried to keep it simple so here is the code: the code for for the pseudo random nums. library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity random_gen is generic ( width : integer := 32 ); port ( clk : in std_logic; random_num : out std_logic_vector (width-1 downto 0) --output vector ); end random_gen; architecture Behavioral of random_gen is begin process(clk) variable rand_temp : std_logic_vector(width-1 downto 0):=(width-1 => '1',others => '0'); variable temp : std_logic := '0'; begin if(rising_edge(clk)) then temp := rand_temp(width-1) xor rand_temp(width-2); rand_temp(width-1 downto 1) := rand_temp(width-2 downto 0); rand_temp(0) := temp; end if; random_num <= rand_temp; end process; end Behavioral; the code for the ALU : LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity ALU_32 is port( A: in STD_LOGIC_VECTOR (31 downto 0); B: in STD_LOGIC_VECTOR (31 downto 0); CHOICE: in STD_LOGIC_VECTOR (2 downto 0); OUTPUT: out STD_LOGIC_VECTOR (31 downto 0)); end alu_32; architecture Behavioral of ALU_32 is begin process (choice) begin case choice is when "000" => output (31 downto 0) <= a+b ; when "001" => output (31 downto 0) <= a-b ; when "010" => output (31 downto 0) <= not a ; when "011" => output (31 downto 0) <= a xor b ; when "100" => output (31 downto 0) <= a and b ; when "101" => output (31 downto 0) <= a or b ; when "110" => output (31 downto 0) <= a nand b; when "111" => output (31 downto 0) <= a nor b; when others => null; end case; end process; end Behavioral; the other component is just a simple comparator that compares the output of 2 ALU's that get the same input , when they are not equal it raises a flag. this flag is the output of the module. if you have some other good idea how to implement such a thing i'll be happy to hear since I'm not experienced and beside this great forum I don't really have anything to consult with. thanks, Yaniv

I suspect that the way you are using the variables means that it thinks it doesnt need the value from clock cycle to clock cycle, meaning random_num is always '0'. Or it could be because you have the random_num output outside of the clock. Either way, I would use signals instead of variables. but for a first attempt, try re-arranging the code like this: process(clk) variable rand_temp : std_logic_vector(width-1 downto 0):=(width-1 => '1',others => '0'); variable temp : std_logic := '0'; begin if(rising_edge(clk)) then random_num <= rand_temp; temp := rand_temp(width-1) xor rand_temp(width-2); rand_temp(width-1 downto 1) := rand_temp(width-2 downto 0); rand_temp(0) := temp; end if; end process;

synthsis problem | Altera Community

18 Replies

Altera_Forum
Honored Contributor
15 years ago
a signal called " inclk0" , the default input clock ...
now i compiled it and it even didn't use the pll so you're probably right ,
How do I fix it?

thank you very much for all your help ...
Altera_Forum
Honored Contributor
15 years ago
you need to connect the inclk0 to a pin on the device! Inclk0 is the input port of the PLL. You need to connect this to a pin on the chip, and provide that pin with an oscillator (this is the clock) on your actual hardware.
Altera_Forum
Honored Contributor
15 years ago
already tried it... didn't work ( just to be sure ,is the symbol for clk pins is a step symbol ?)
Altera_Forum
Honored Contributor
15 years ago
hi ,

does anyone has any idea how to fix it?
I'm starting to be desperate ...
I dont mind even send it the entire project so U can review it...
Altera_Forum
Honored Contributor
15 years ago
In the assignments editor - how do I force the compiler to implement code (or entity) ?
thanks...
Altera_Forum
Honored Contributor
15 years ago
Hi ys0011,

Send me the project and I'll review it.

Cheers, Ton
Altera_Forum
Honored Contributor
15 years ago
For all readers interested in the review:
In his design, Yaniv used a comparator, but the two paths to the comparator were identical and thus optimized away. So there was no logic left to drive for the clock.

Bye, Ton
Altera_Forum
Honored Contributor
15 years ago
Is it correct of the clock wave? How frequency of the clock? Is it locked of the Pll?

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synthsis problem

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