Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

synthsis problem

Hi , for a university project I programed ( VHDL) some program to test FPGA errors under very noisy environments . the structure is built of (pseudo) random number generator--->simple ALU...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

already tried it... didn't work ( just to be sure ,is the symbol for clk pins is a step symbol ?)