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Altera_Forum
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12 years ago

Synthesizable vs non-synthesizable code

Hi, I have a question regarding how the below piece of code can be made synthesizable. The simulation works fine in modelsim. But when I run Analysis and Synthesis in Quartus I get the followi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hello kaz,

Since I cannot attach the original code I have written something very similar to it and I have attached it. The module test.v is the one under question.

The wires wire1, wire2, wire3 are directly dependent on the inputs where as test_out is dependent on wire1, wire2, wire3.

Kindly let me know your thoughts on this.

Thank you.