Synthesizable vs non-synthesizable code

Thanks for the reply Kaz.. I should have been more articulate when I asked the question . It was just a portion of the code that I had written above and not the code itslef. My code is more like this...

<verilog statements>

....

...

always (@posedge clock)

begin

if (sig_1 == 5'b11111)

begin

output <= 2'd0;

end

else if (sig_2 == 5'b11111)

begin

output <= 2'd1;

end

else if (sig_3 == 5'b11111)

begin

output <= 2'd2;

end

end

......

.....

<verilog statements>

This 'output' signal is connected to the input of another module. And I am getting this warning msg : warning (10034): output port at <> has no driver .