Synthesizable vs non-synthesizable code

The whole purpose of logic design is to take input(s) from outside module and drive output(s) to other modules and according to your internal logic decisions.

I am not aware if an input-less design is ever possible in fpgas. Moreover if your outputs are driven once only and undefined otherwise then the compiler simply is saying you don't need to do anything and the output stays floating with any empty fpga. So at least get clock input, then an internal counter and drive output based on count value assigning to it high or low.