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Altera_Forum
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16 years ago

synthesisable "wait" statement?

Hi, I found that it is not possible to synthesis VHDL wait statement in quartus 2. Is there any other alternative for this. What I am trying to do, is to generate some signals as shown in atta...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

The wait statement was never put in to be synthesisable. It is there for modeling purposes only.

The easiest (and with FPGAs, probably the only way) is to use a clock and then you can syncronise all logic. This means you can garantee waiting times through counting clock cycles.